1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device and fabrication method therefor that prevents electrostatic discharge failure withstand voltage drop in a fabrication method of a semiconductor device using a self-aligned silicide CMOS process.
2. Description of the Conventional Art
A self-aligned silicide (salicide) source/drain process is widely applied to most of the currently used integrated circuit devices to increase the operation speed of a circuit. That is, the overall resistance of a semiconductor device can be reduced by forming a silicide which has low resistance on source/drain regions, thus accordingly achieving high-speed operation of the semiconductor device.
However, an electrostatic discharge (ESD) failure voltage of an ESD protecting device of a semiconductor device which is fabricated by the salicide source/drain process is considerably lower than an ESD failure voltage of a semiconductor device which is fabricated by a general non-silicide source/drain process, which results in deterioration of a product, meaning that the salicide source/drain process has a reverse effect on the ESD protecting characteristic. Since a drain of the ESD protecting device of the non-silicide source/drain structure has an appropriate resistance value, when a high ESD failure voltage is applied thereto, the drain thereof operates as a ballast and thus a withstand voltage to the ESD is high. But, the drain resistance decreases by forming the silicide on the source/drain regions and eventually no ballasting effect of the drain is shown, thereby reducing the ESD failure voltage. Accordingly, to solve such a problem, there is provided a method of fabricating a semiconductor device wherein a silicide blocking portion is formed with respect to the whole ESD protecting device when forming a salicide layer on the source/drain regions, so that the suicide may not be formed on the ESD device.
In other words, the salicide source/drain process is only performed to elements constituting an internal circuit among constituent circuits of the integrated circuit and a silicide blocking layer is formed on the ESD protecting device, thereby forming the non-silicide source/drain structure. The fabrication method of the conventional semiconductor device will be explained with reference to FIGS. 1A through 1D.
In FIGS. 1A through 1D, a transistor which is shown in the left-hand side of each dotted line is an internal circuit transistor, while a transistor in the right-hand side is an ESD transistor, and a connecting structure of the internal circuit and the in ESD transistor is not illustrated to briefly explain the fabrication method therefor. First, as shown in FIG. 1A, a device isolation region 2 is formed by applying a shallow trench process to a semiconductor substrate 1. Here, the shallow trench process is a device isolating method wherein a shallow trench is formed at a portion where the device isolation region of the semiconductor substrate is to be formed and an insulating film such as an oxide film is filled in the trench, so that adjacent devices are not electrically connected.
Next, the internal circuit transistor and the ESD transistor are formed at the semiconductor substrate 1 by a well-known MOS transistor fabrication method. That is, gate insulating films 3 are formed on the semiconductor substrate 1, a polysilicon layer is formed on the gate insulating films 3 and then selectively patterned, for thereby forming polysilicon gate electrodes 4. Next, lightly doped drains (LDD) 5 are formed by doping low density impurity ions into the semiconductor substrate 1 by a self-aligned method using the polysilicon gate electrodes 4 as masks, and an insulating film at a uniform thickness is formed over the entire resultant surface of the semiconductor substrate 1 and the insulating film is etched by an anisotropic etching process, thereby forming sidewall spacers 6 on side surfaces of the polysilicon gate electrodes 4. Next, source/drain regions 7 are formed by implanting impurity ions into the semiconductor substrate 1 using the sidewall spacers 6 and the polysilicon gate electrodes 4 as masks. As shown in FIG. 1B, an insulating film which serves as a protection film 8 is deposited over the resultant structure of the semiconductor substrate 1 and, as shown in FIG. 1C, a portion of the protection film 8 corresponding to a portion where the internal circuit transistor is to be formed is selectively etched and removed, so that the protection film 8 only remains on the ESD transistor. Then, as shown in FIG. 1D, a self-aligned silicide 9 is formed on the source/drain regions 7 and the polysilicon gate electrode 4 of the internal circuit transistor region by the well-known self-aligned method.
However, the conventional fabrication method for the semiconductor device has several disadvantages.
First, since the protection film must be formed for controlling the formation of the salicide layer, the deposition and the photo-etching process are additionally provided, so that the fabrication process is complicated. Second, because the process for depositing the protection film is accomplished after fabricating the transistor, the characteristics of the transistor which has been previously fabricated are changed due to a heat treatment process which accompanies the depositing process. Third, when removing the protection film formed on the internal circuit transistor, a field oxide film of the device isolation region is damaged due to over-etching, which results in deterioration of the electrical characteristics, such as radical increase in junction leakage current. Finally, when a material of the protection film is oxide, oxygen permeates through the source/drain regions and the polysilicon gate electrodes of the internal circuit transistor which makes it difficult to perform the silicide forming process.